Package carrier and manufacturing method thereof

ABSTRACT

A manufacturing method of a package carrier is provided. An insulation substrate having an upper surface, a lower surface, plural cavities located at the lower surface and plural through holes passing through the insulation substrate and respectively communicating with the cavities is provided. Plural vias is defined by the cavities and the through holes. A conductive material filling up the vias is formed to define plural conductive posts. An insulation layer having a top surface and plural blind vias extending from the top surface to the conductive posts is formed on the upper surface. A patterned circuit layer filling up the blind vias, being connected to the conductive posts and exposing a portion of the top surface is formed on the top surface. A solder mask layer is formed on the patterned circuit layer and has plural openings exposing a portion of the patterned circuit layer to define plural pads.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 101128619, filed on Aug. 8, 2012. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND

1. Field of the Invention

The invention relates to a package structure and a manufacturing methodthereof, and more particularly, to a package carrier and a manufacturingmethod thereof.

2. Description of Related Art

The purpose of chip package is to protect exposed chips, to reducecontact density in a chip, and to provide good thermal dissipation forchips. A leadframe serving as a carrier of a chip is usually employed ina conventional wire bonding technique. As contact density in a chipgradually increases, the leadframe which is unable to satisfy currentdemands on the high contact density is replaced by a package carrierwhich can achieve favorable contact density. Besides, the chip ispackaged onto the package carrier by conductive media, such asconductive wires or bumps.

Take a light-emitting diode (LED) package structure commonly used atpresent time as an example. A LED chip has to be packaged before used,and the LED chip generates a large amount of heat when emitting light.Therefore, if the heat generated by the LED chip cannot be dissipatedand keeps accumulating in the LED package structure, a temperature ofthe LED package structure would keep rising. In this way, the LED chipmay be overheated, which causes luminance decay and shortens operatinglife thereof or even causes permanent damage in server cases.

As the integration level of integrated circuits increases, due to themismatch of thermal expansion coefficient between the LED chip and thepackage carrier, the phenomena of thermal stress and warpage become moreand more severe, and that causes the reliability between the LED chipand the package carrier to decrease. Therefore, in addition to enhancingthe light extraction efficiency, the current package technology focuseson decreasing the thermal stress of the package structure to increasethe operating life and the reliability of the package structure.

SUMMARY OF THE INVENTION

The invention provides a package carrier which effectively decreases athermal expansion difference when the package carrier carries a heatingelement and increases a using reliability.

The invention provides a manufacturing method of a package carrier formanufacturing the aforementioned package carrier.

The invention provides a manufacturing method of a package carrier. Themanufacturing method includes the following steps. An insulationsubstrate is provided. The insulation substrate has an upper surface, alower surface opposite to the upper surface, a plurality of cavities anda plurality of through holes. The cavities are located at the lowersurface, and the through holes pass through the insulation substrate andrespectively communicate with the cavities to define a plurality ofvias. A conductive material is formed in the vias, wherein theconductive material fills up the vias to define a plurality ofconductive posts. An insulation layer is formed on the upper surface ofthe insulation substrate. The insulation layer has a top surfacerelatively far from the upper surface of the insulation substrate and aplurality of blind vias extending from the top surface to the conductiveposts. A patterned circuit layer is formed on the top surface of theinsulation layer. The patterned circuit layer fills up the blind viasand is connected to the conductive posts. The patterned circuit layerexposes a portion of the top surface of the insulation layer. A soldermask layer is formed on the patterned circuit layer. The solder masklayer covers the patterned circuit layer and the exposed portion of thetop surface of the insulation layer. The solder mask layer has aplurality of openings, wherein the openings expose a portion of thepatterned circuit layer so as to define a plurality of pads.

In an embodiment of the invention, a material of the insulationsubstrate includes ABF resin, polymeric materials, silicon fillers orepoxy resin.

In an embodiment of the invention, a method of forming the cavities ofthe insulation substrate includes laser drilling or injection molding.

In an embodiment of the invention, a method of forming the through holesof the insulation substrate includes laser drilling.

In an embodiment of the invention, steps of forming the conductivematerial in the vias include: performing an electroless plating processto form the conductive material on the upper surface, the lower surfaceand in the vias of the insulation substrate, wherein the conductivematerial covers the upper surface and the lower surface of theinsulation substrate and fills up the vias; and removing a portion ofthe conductive material on the upper surface and the lower surface ofthe insulation substrate to expose the upper surface and the lowersurface of the insulation substrate so as to define the conductiveposts.

In an embodiment of the invention, each of the conductive posts has afirst surface and a second surface opposite to each other. The firstsurface of each of the conductive posts and the upper surface of theinsulation substrate are coplanar, and the second surface of each of theconductive posts and the lower surface of the insulation substrate arecoplanar.

In an embodiment of the invention, a method of forming the insulationlayer includes thermal compression bonding.

In an embodiment of the invention, a material of the insulation layerincludes ABF resin, polymeric materials, silicon fillers or epoxy resin.

In an embodiment of the invention, a method of forming the blind vias ofthe insulation layer includes laser drilling.

In an embodiment of the invention, a method of forming the patternedcircuit layer includes electroless plating or a semi-additive process.

In an embodiment of the invention, the manufacturing method furtherincludes forming a surface treatment layer on the pads after the soldermask layer is formed.

In an embodiment of the invention, the surface treatment layer includesan electroplated gold layer, an electroplated silver layer, a reducedgold layer, a reduced silver layer, an electroplatednickel-palladium-gold layer, a nickel-palladium-gold layer or an organicsolderability preservatives (OSP) layer.

The invention provides a package carrier adapted for carrying a heatingelement. The package carrier includes an insulation substrate, aplurality of conductive posts, an insulation layer, a patterned circuitlayer and a solder mask layer. The insulation substrate has an uppersurface, a lower surface opposite to the upper surface, a plurality ofcavities and a plurality of through holes. The cavities are located atthe lower surface, and the through holes pass through the insulationsubstrate and respectively communicate with the cavities to define aplurality of vias. The conductive posts are respectively disposed in thevias, and each of the conductive posts has a first surface and a secondsurface opposite to each other. The first surface of each of theconductive posts and the upper surface of the insulation substrate arecoplanar, and the second surface of each of the conductive posts and thelower surface of the insulation substrate are coplanar. An insulationlayer is disposed on the upper surface of the insulation substrate. Theinsulation layer has a top surface relatively far from the upper surfaceof the insulation substrate and a plurality of blind vias extending fromthe top surface to the conductive posts. The patterned circuit layer isdisposed on the top surface of the insulation layer and exposes aportion of the top surface of the insulation layer. The patternedcircuit layer fills up the blind vias and is connected to the conductiveposts. A solder mask layer is disposed on the patterned circuit layer.The solder mask layer covers the patterned circuit layer and the exposedportion of the top surface of the insulation layer. The solder masklayer has a plurality of openings, wherein the openings expose a portionof the patterned circuit layer so as to define a plurality of pads, andthe heating element is disposed on the pads.

In an embodiment of the invention, the package carrier further includesa surface treatment layer disposed on the pads.

In an embodiment of the invention, the surface treatment layer includesan electroplated gold layer, an electroplated silver layer, a reducedgold layer, a reduced silver layer, an electroplatednickel-palladium-gold layer, a nickel-palladium-gold layer or an OSPlayer.

Based on the above, the package carrier of the invention uses aninsulation substrate with an ideal thermal expansion coefficient as acore. Therefore, when the package carrier is used in the package of aheating element (such as a chip) subsequently, a difference in thermalexpansion coefficient between the package carrier and the heatingelement carried on the package carrier is reduced effectively, whichprevents a stress between the heating element and the insulationsubstrate from increasing because of a too great difference in thermalexpansion coefficient therebetween and effectively prevents the peelingand damage of the heating element from happening, thereby enhancing theusing reliability of the package carrier.

In order to make the aforementioned features and advantages of theinvention more comprehensible, embodiments accompanying figures aredescribed in details below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide further understandingand are incorporated in and constitute a part of this specification. Thedrawings illustrate exemplary embodiments and, together with thedescription, serve to explain the principles of the invention.

FIGS. 1A to 1H are schematic cross-sectional views of a manufacturingmethod of a package carrier according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view of the package carrier ofFIG. 1H carrying a heating element.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A to 1H are schematic cross-sectional views of a manufacturingmethod of a package carrier according to an embodiment of the invention.According to the manufacturing method of the package carrier of thepresent embodiment, referring to FIG. 1A, an insulation substrate 110 isprovided first. The insulation substrate 110 has an upper surface 112, alower surface 114 opposite to the upper surface 112 and a plurality ofcavities 116, wherein the cavities 116 are located at the lower surface114 of the insulation substrate 110. Herein, a method of forming thecavities 116 of the insulation substrate 110 is, for example, laserdrilling or injection molding. In addition, a material of the insulationsubstrate 110 is, for example, ABF resin, polymeric materials, siliconfillers or epoxy resin.

Then, referring to FIG. 1B, through holes 118 passing through theinsulation substrate 110 and respectively communicating with thecavities 116 are formed on the upper surface 112 of the insulationsubstrate 110. Herein, each of the through holes 118 and thecorresponding cavity 116 define a via T, and a diameter of each of thethrough holes 118 is substantially less than a diameter of each of thecavities 116. In addition, a method of forming the through holes 118 is,for example, laser drilling.

Then, referring to FIG. 1C, an electroless plating process is performedto form a conductive material 120 on the upper surface 112, the lowersurface 114 and in the vias T of the insulation substrate 110. Theconductive material 120 covers the upper surface 112 and the lowersurface 114 of the insulation substrate 110 and fills up the vias T,wherein the conductive material 120 is copper, for example.

Then, referring to FIG. 1D, a portion of the conductive material 120 onthe upper surface 112 and the lower surface 114 of the insulationsubstrate 110 is removed to expose the upper surface 112 and the lowersurface 114 of the insulation substrate 110 so as to define a pluralityof conductive posts 120 a. Herein, each of the conductive posts 120 ahas a first surface 122 and a second surface 124 opposite to each other.The first surface 122 of each of the conductive posts 120 a and theupper surface 112 of the insulation substrate 110 are substantiallycoplanar, and the second surface 124 of each of the conductive posts 120a and the lower surface 114 of the insulation substrate 110 aresubstantially coplanar.

Then, referring to FIG. 1E, an insulation layer 130 is formed on theupper surface 112 of the insulation substrate 110, wherein theinsulation layer 130 has a top surface 132 relatively far from the uppersurface 112 of the insulation substrate 110. Herein, a method of formingthe insulation layer 130 is thermal compression bonding, for example. Inaddition, a material of the insulation layer 130 is, for example, ABFresin, polymeric materials, silicon fillers or epoxy resin.

Then, referring to FIG. 1F, blind vias B extending from the top surface132 of the insulation layer 130 to the conductive posts 120 a areformed, wherein the blind vias B respectively expose the first surface122 of the conductive posts 120 a. Herein, a method of forming the blindvias B of the insulation layer 130 is laser drilling, for example.

Then, referring to FIG. 1G, a patterned circuit layer 140 is formed onthe top surface 132 of the insulation layer 130, wherein the patternedcircuit layer 140 fills up the blind vias B and is structurally andelectrically connected to the conductive posts 120 a, and the patternedcircuit layer 140 exposes a portion of the top surface 132 of theinsulation layer 130. Herein, a method of forming the patterned circuitlayer 140 is, for example, electroless plating or a semi-additiveprocess, which is not limited herein.

Finally, referring to FIG. 1H, a solder mask layer 150 is formed on thepatterned circuit layer 140, wherein the solder mask layer 150 coversthe patterned circuit layer 140 and the exposed portion of the topsurface 132 of the insulation layer 130. Herein, the solder mask layer150 has a plurality of openings 152, wherein the openings 152 expose aportion of the patterned circuit layer 140 to define a plurality of pads142. In addition, the manufacturing method of the package carrier of thepresent embodiment may further include forming a surface treatment layer160 on the pads 142, wherein the surface treatment layer 160 is, forexample, an electroplated gold layer, an electroplated silver layer, areduced gold layer, a reduced silver layer, an electroplatednickel-palladium-gold layer, a nickel-palladium-gold layer or an organicsolderability preservatives (OSP) layer. Herein, a method of forming thesurface treatment layer 160 is, for example, electro-plating orelectroless plating, which is not limited herein. To this point, themanufacturing of the package carrier 100 is completed.

Regarding structures, referring to FIG. 1H again, the package carrier100 of the present embodiment includes the insulation substrate 110, theconductive posts 120 a, the insulation layer 130, the patterned circuitlayer 140 and the solder mask layer 150. The insulation substrate 110has an upper surface 112, a lower surface 114 opposite to the uppersurface 112, a plurality of cavities 116 and a plurality of throughholes 118, wherein the diameter of each of the through holes 118 issubstantially less than the diameter of each of the cavities 116. Thecavities 116 are located at the lower surface 114, and the through holes118 pass through the insulation substrate 110 and respectivelycommunicate with the cavities 116 to define the vias T. The conductiveposts 120 a are respectively disposed in the vias T, and each of theconductive posts 120 a has the first surface 122 and the second surface124 opposite to each other. The first surface 122 of each of theconductive posts 120 a and the upper surface 112 of the insulationsubstrate 110 are substantially coplanar, and the second surface 124 ofeach of the conductive posts 120 a and the lower surface 114 of theinsulation substrate 110 are substantially coplanar. The insulationlayer 130 is disposed on the upper surface 112 of the insulationsubstrate 110. The insulation layer 130 has the top surface 132relatively far from the upper surface 112 of the insulation substrate110 and the blind vias B extending from the top surface 132 to theconductive posts 120 a. The patterned circuit layer 140 is disposed onthe top surface 132 of the insulation layer 130 and exposes a portion ofthe top surface 132 of the insulation layer 130. The patterned circuitlayer 140 fills up the blind vias B and is connected to the conductiveposts 120 a. The solder mask layer 150 is disposed on the patternedcircuit layer 140, and the solder mask layer 150 covers the patternedcircuit layer 140 and the exposed portion of the top surface 132 of theinsulation layer 130. The solder mask layer 150 has the plurality ofopenings 152, wherein the openings 152 expose a portion of the patternedcircuit layer 140 to define the pads 142. In addition, the packagecarrier 100 of the present embodiment may further include the surfacetreatment layer 160 disposed on the pads 142, wherein the surfacetreatment layer 160 is, for example, an electroplated gold layer, anelectroplated silver layer, a reduced gold layer, a reduced silverlayer, an electroplated nickel-palladium-gold layer, anickel-palladium-gold layer or an OSP layer.

Since the present embodiment uses the insulation substrate 110 as thecore of the package carrier 100, wherein the insulation substrate 110has an ideal thermal expansion coefficient (similar to a thermalexpansion coefficient of a heating element used subsequently, forexample), when the package carrier 100 is used in the package of aheating element (not shown) subsequently, a difference in thermalexpansion coefficient between the package carrier 100 and the heatingelement carried on the package carrier 100 is reduced, which prevents astress between the heating element and the insulation substrate 110 fromincreasing because of a too great difference in thermal expansioncoefficient therebetween and effectively prevents the peeling and damageof the heating element from happening, thereby enhancing the usingreliability of the package carrier 100. In addition, since the patternedcircuit layer 140 of the present embodiment is formed by electrolessplating or by the semi-additive process, a width of the patternedcircuit layer 140 is able to meet the specification of fine circuits.

FIG. 2 is a schematic cross-sectional view of the package carrier ofFIG. 1H carrying a heating element. In the present embodiment, thepackage carrier 100 is adapted for carrying a heating element 200,wherein the heating element 200 is disposed on the surface treatmentlayer 160 on the pads 142 exposed by the openings 152 of the solder masklayer 150. The heating element 200 is, for example, an electronic chipor a photoelectric device but is not limited thereto. For example, theelectronic chip may be an integrated circuit chip, such as a single chip(like a graphic chip, a memory chip, or a semiconductor chip) or a chipmodule. The photoelectric device is, for example, a LED, a laser diodeor a gas-discharge light source. Herein, the heating element 200 being aLED serves as an example.

In detail, the heating element 200 (such as a semiconductor chip) may beelectrically connected to the surface treatment layer 160 by flip chipbonding. Since the present embodiment uses the insulation substrate 110with an ideal thermal expansion coefficient as the core of the packagecarrier 100, a difference in thermal expansion coefficient between thepackage carrier 100 and the heating element 200 is gradually reduced. Inthis way, a stress between the heating element 200 and the packagecarrier 100 can be prevented from increasing because of a too greatdifference in thermal expansion coefficient therebetween, and thepeeling and damage of the heating element 200 is effectively preventedfrom happening, thereby enhancing the using reliability of the packagecarrier 100. Furthermore, when the heating element 200 is disposed onthe package carrier 100, heat generated by the heating element 200 istransmitted to the outside rapidly through the surface treatment layer160, the patterned circuit layer 140 and the conductive posts 120 a. Inthis way, the package carrier 100 of the present embodiment effectivelydissipates the heat generated by the heating element 200, therebyenhancing the using efficiency and operating life of the heating element200. In addition, a plurality of solder balls 210 may be disposed on thelower surface 114 of the insulation substrate 110 of the package carrier100 of the present embodiment, and the package carrier 100 may beelectrically connected to an external circuit (not shown) through thesolder balls 210, which effectively enhances the application of thepackage carrier 100.

In summary of the above, the package carrier of the invention uses aninsulation substrate with an ideal thermal expansion coefficient as acore. Therefore, when the package carrier is used in the package of aheating element (such as a chip) subsequently, a difference in thermalexpansion coefficient between the package carrier and the heatingelement carried on the package carrier is reduced effectively, whichprevents a stress between the heating element and the insulationsubstrate from increasing because of a too great difference in thermalexpansion coefficient therebetween and effectively prevents the peelingand damage of the heating element from happening, thereby enhancing theusing reliability of the package carrier.

Although the invention has been described with reference to the aboveembodiments, they are not intended to limit the invention. It isapparent to people of ordinary skill in the art that modifications andvariations to the invention may be made without departing from thespirit and scope of the invention. In view of the foregoing, theprotection scope of the invention will be defined by the appendedclaims.

What is claimed is:
 1. A manufacturing method of a package carrier,comprising: providing an insulation substrate, the insulation substratehaving an upper surface, a lower surface opposite to the upper surface,a plurality of cavities and a plurality of through holes, wherein thecavities are located at the lower surface, and the through holes passthrough the insulation substrate and respectively communicate with thecavities to define a plurality of vias; forming a conductive material inthe vias, wherein the conductive material fills up the vias to define aplurality of conductive posts; forming an insulation layer on the uppersurface of the insulation substrate, wherein the insulation layer has atop surface relatively far from the upper surface of the insulationsubstrate and a plurality of blind vias extending from the top surfaceto the conductive posts; forming a patterned circuit layer on the topsurface of the insulation layer, wherein the patterned circuit layerfills up the blind vias and is connected to the conductive posts, andthe patterned circuit layer exposes a portion of the top surface of theinsulation layer; and forming a solder mask layer on the patternedcircuit layer, the solder mask layer covering the patterned circuitlayer and the exposed portion of the top surface of the insulationlayer, the solder mask layer having a plurality of openings, wherein theopenings expose a portion of the patterned circuit layer to define aplurality of pads.
 2. The manufacturing method of the package carrier asrecited in claim 1, wherein a material of the insulation substrateincludes ABF resin, polymeric materials, silicon fillers or epoxy resin.3. The manufacturing method of the package carrier as recited in claim1, wherein a method of forming the cavities of the insulation substrateincludes laser drilling or injection molding.
 4. The manufacturingmethod of the package carrier as recited in claim 1, wherein a method offorming the through holes of the insulation substrate includes laserdrilling.
 5. The manufacturing method of the package carrier as recitedin claim 1, wherein steps of forming the conductive material in the viascomprise: performing an electroless plating process to form theconductive material on the upper surface, the lower surface and in thevias of the insulation substrate, wherein the conductive material coversthe upper surface and the lower surface of the insulation substrate andfills up the vias; and removing a portion of the conductive material onthe upper surface and the lower surface of the insulation substrate toexpose the upper surface and the lower surface of the insulationsubstrate to define the conductive posts.
 6. The manufacturing method ofthe package carrier as recited in claim 1, wherein each of theconductive posts has a first surface and a second surface opposite toeach other, the first surface of each of the conductive posts and theupper surface of the insulation substrate are coplanar, and the secondsurface of each of the conductive posts and the lower surface of theinsulation substrate are coplanar.
 7. The manufacturing method of thepackage carrier as recited in claim 1, wherein a method of forming theinsulation layer includes thermal compression bonding.
 8. Themanufacturing method of the package carrier as recited in claim 1,wherein a material of the insulation layer includes ABF resin, polymericmaterials, silicon fillers or epoxy resin.
 9. The manufacturing methodof the package carrier as recited in claim 1, wherein a method offorming the blind vias of the insulation layer includes laser drilling.10. The manufacturing method of the package carrier as recited in claim1, wherein a method of forming the patterned circuit layer includeselectroless plating or a semi-additive process.
 11. The manufacturingmethod of the package carrier as recited in claim 1, further comprising:forming a surface treatment layer on the pads after the solder masklayer is formed.
 12. The manufacturing method of the package carrier asrecited in claim 11, wherein the surface treatment layer comprises anelectroplated gold layer, an electroplated silver layer, a reduced goldlayer, a reduced silver layer, an electroplated nickel-palladium-goldlayer, a nickel-palladium-gold layer or an organic solderabilitypreservatives (OSP) layer.
 13. A package carrier adapted for carrying aheating element, the package carrier comprising: an insulation substratewhich has an upper surface, a lower surface opposite to the uppersurface, a plurality of cavities and a plurality of through holes,wherein the cavities are located at the lower surface, and the throughholes pass through the insulation substrate and respectively communicatewith the cavities to define a plurality of vias; a plurality ofconductive posts respectively disposed in the vias, each of theconductive posts having a first surface and a second surface opposite toeach other, wherein the first surface of each of the conductive postsand the upper surface of the insulation substrate are coplanar, and thesecond surface of each of the conductive posts and the lower surface ofthe insulation substrate are coplanar; an insulation layer disposed onthe upper surface of the insulation substrate, wherein the insulationlayer has a top surface relatively far from the upper surface of theinsulation substrate and a plurality of blind vias extending from thetop surface to the conductive posts; a patterned circuit layer disposedon the top surface of the insulation layer and exposing a portion of thetop surface of the insulation layer, the patterned circuit layer fillingup the blind vias and being connected to the conductive posts; and asolder mask layer disposed on the patterned circuit layer, the soldermask layer covering the patterned circuit layer and the exposed portionof the top surface of the insulation layer, the solder mask layer havinga plurality of openings, wherein the openings expose a portion of thepatterned circuit layer to define a plurality of pads, and the heatingelement is disposed on the pads.
 14. The package carrier as recited inclaim 13, further comprising a surface treatment layer disposed on thepads.
 15. The package carrier as recited in claim 14, wherein thesurface treatment layer comprises an electroplated gold layer, anelectroplated silver layer, a reduced gold layer, a reduced silverlayer, an electroplated nickel-palladium-gold layer, anickel-palladium-gold layer or an organic solderability preservativeslayer.